Senior Full Stack Engineer (Data Pipeline Team)

• Design efficient algorithms and data structures in C++

• Profile and optimize C++ code

• Work with open-source tools and frameworks

Industry

Level

Autopilot

Location

Mountain View, CA

Senior

自动驾驶高级算法工程师（感知方向）

• 负责计算机视觉或深度学习算法相关的前沿技术研发工作

• 负责图像或三维点云中的目标检测、跟踪，图像理解等相关算法研发工作

• 负责SLAM、VIO等相关算法的研发工作

• 负责camera、lidar、radar等多传感器融合算法研发工作 

Industry

Level

Autopilot

Location

Beijing, China / SV, US

Senior

Software Engineer

• Programming experience with at least one modern language such as Python, Java, C++, including object-oriented design

• Strong understanding of Software Development Lifecycle (SDLC)

• Demonstrate knowledge of database structure and working practice of reporting tools

• Learning quickly through rapid and incremental prototyping

• Experience with GIT source control management

• BS Degree in Information Systems, Computer Science or related field 

Industry

Level

Voice Recoginition

Location

Santa Clara, CA

Junior

NAND Logic Design Engineer

• This Position is part of 3D NAND logic design team.

• Candidate will be a technical individual contributor in Logic design include on-chip controller, NAND interface, Functional Block and FW development.

Industry

Level

R&D

Location

San Jose, CA

Senior

Technical Recruiter

• Source, qualify, and present a solid, diverse slate of candidates for every open position to which you are assigned.

• Collaborate and build staffing plans proactively with the assigned business group to enable them to achieve resource hiring requirements. 

• Demonstrate the ability to articulate both positive and negative feedback to ALL candidates in a professional manner. 

• Has in-depth knowledge of the business segment strategic resource objectives and the talent acquisition functional area. Participates with line management in developing talent resource objectives. 

Industry

Level

Human Resource

Location

Santa Clara, CA

Junior

RTL Designer

• Design RTL for our CPU-centric Machine Learning ASIC chip - Optimize timing and power consumption.

• Support functionality debug in simulation and emulation.

• Write timing/power constraint for the design

Industry

Level

AI Chip

Location

Santa Clara, CA

Senior

自动驾驶预测决策规划算法工程师

• 负责自动驾驶汽车预测决策规划系统的规划、研发、调试工作。

• 探索适合目标领域的模型算法,解决自动驾驶预测决策规划领域的实际问题。

• 设计核心驾驶场景处理策略,完成相关算法研发和效果验证。

Industry

Level

Autopilot

Location

Beijing, China

Senior

Autonomous Software Stack Test Lead

• Lead the test engineering team in defining the software test strategy to ensure functionality, reliability, and accuracy performance for the autonomous software stack

Industry

Level

Autopilot

Location

Mountain View, CA

Senior

Machine Learning Engineer (Perception Team)

• Work with the team to develop new deep learning algorithms and applications

• Run experiments on mainstream machine learning frameworks, learn, and iterate with the team.

Industry

Level

Autopilot

Location

Mountain View, CA

Senior

资深研发工程师（超声波雷达方向）

• 超声波雷达信号采集，系统集成

• 自动驾驶任务中超声波雷达测距算法、车位检测算法开发、改进、测试验证

Industry

Level

Autopilot

Location

Beijing, China

Senior

智慧交通产品架构师

• 负责规划、设计最前沿的智能交通的产品与服务

• 负责研究交通行业智能化需求与发展趋势，理解和分解市场业务场景，落实到产品规划与设计、

       效果跟踪与评估，始终保持市场中的领先地位

Industry

Level

Autopilot

Location

Beijing, China

Senior

Design Verification Engineer

• Verifying the design, architecture and micro-architecture using advanced verification methodologies.

• Defining the verification scope and contributing to the development of the verification infrastructure.

• Collaborating with architects, designers, and software engineers across sites to accomplish verification targets 

Industry

Level

AI Chip

Location

Santa Clara, CA

Senior

AI Accelerator Software Systems Engineer

• Implement and debug existing ML models and kernels, including TensorFlow kernels, targeting OURS hardware.

• Optimize models for latency, throughput, power, and memory footprint.

• Optimize power, performance, and memory footprint of Linux build for OURS hardware  

Industry

Level

AI Chip

Location

Santa Clara, CA

Senior

Analog Design Engineer

• In this position, the individual will design analog block and conduct full chip simulation for the cutting-edge 3D NAND flash chip.

Industry

Level

AI Chip

Location

San Jose, CA

Senior