Design efficient algorithms and data structures in C++
Profile and optimize C++ code
Work with open-source tools and frameworks
Mountain View, CA
Beijing, China / SV, US
Programming experience with at least one modern language such as Python, Java, C++, including object-oriented design
Strong understanding of Software Development Lifecycle (SDLC)
Demonstrate knowledge of database structure and working practice of reporting tools
Learning quickly through rapid and incremental prototyping
Experience with GIT source control management
BS Degree in Information Systems, Computer Science or related field
Santa Clara, CA
This Position is part of 3D NAND logic design team.
Candidate will be a technical individual contributor in Logic design include on-chip controller, NAND interface, Functional Block and FW development.
San Jose, CA
Source, qualify, and present a solid, diverse slate of candidates for every open position to which you are assigned.
Collaborate and build staffing plans proactively with the assigned business group to enable them to achieve resource hiring requirements.
Demonstrate the ability to articulate both positive and negative feedback to ALL candidates in a professional manner.
Has in-depth knowledge of the business segment strategic resource objectives and the talent acquisition functional area. Participates with line management in developing talent resource objectives.
Design RTL for our CPU-centric Machine Learning ASIC chip - Optimize timing and power consumption.
Support functionality debug in simulation and emulation.
Write timing/power constraint for the design
Lead the test engineering team in defining the software test strategy to ensure functionality, reliability, and accuracy performance for the autonomous software stack
Work with the team to develop new deep learning algorithms and applications
Run experiments on mainstream machine learning frameworks, learn, and iterate with the team.
Verifying the design, architecture and micro-architecture using advanced verification methodologies.
Defining the verification scope and contributing to the development of the verification infrastructure.
Collaborating with architects, designers, and software engineers across sites to accomplish verification targets
Implement and debug existing ML models and kernels, including TensorFlow kernels, targeting OURS hardware.
Optimize models for latency, throughput, power, and memory footprint.
Optimize power, performance, and memory footprint of Linux build for OURS hardware
In this position, the individual will design analog block and conduct full chip simulation for the cutting-edge 3D NAND flash chip.